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High Common-Mode Voltage, Difference Amplifier AD629
FEATURES
Improved replacement for: INA117P and INA117KU 270 V common-mode voltage range Input protection to 500 V common mode 500 V differential mode Wide power supply range (2.5 V to 18 V) 10 V output swing on 12 V supply 1 mA maximum power supply current HIGH ACCURACY DC PERFORMANCE 3 ppm maximum gain nonlinearity (AD629B) 20 V/C maximum offset drift (AD629A) 10 V/C maximum offset drift (AD629B) 10 ppm/C maximum gain drift EXCELLENT AC SPECIFICATIONS 77 dB minimum CMRR @ 500 Hz (AD629A) 86 dB minimum CMRR @ 500 Hz (AD629B) 500 kHz bandwidth
FUNCTIONAL BLOCK DIAGRAM
REF(-) 1 -IN
2
21.1k 380k 380k
380k
8 NC 7 +VS 6 OUTPUT
+IN 3 -VS 4
20k
NC = NO CONNECT
Figure 1.
GENERAL DESCRIPTION
The AD629 is a difference amplifier with a very high input, common-mode voltage range. It is a precision device that allows the user to accurately measure differential signals in the presence of high common-mode voltages up to 270 V. The AD629 can replace costly isolation amplifiers in applications that do not require galvanic isolation. The device operates over a 270 V common-mode voltage range and has inputs that are protected from common-mode or differential mode transients up to 500 V. The AD629 has low offset, low offset drift, low gain error drift, low common-mode rejection drift, and excellent CMRR over a wide frequency range. The AD629 is available in low cost, 8-lead PDIP and 8-lead SOIC packages. For all packages and grades, performance is guaranteed over the industrial temperature range of -40C to +85C.
APPLICATIONS
High voltage current sensing Battery cell voltage monitors Power supply current monitors Motor controls Isolation
100
COMMON-MODE REJECTION RATIO (dB)
95
2mV/DIV
85 80 75 70 65 60
00783-002
OUTPUT ERROR (2mV/DIV)
90
00783-001
AD629
5 REF(+)
55 50 20 100 1k FREQUENCY (Hz) 10k
60V/DIV -240 -120 0 120 COMMON-MODE VOLTAGE (V) 240
20k
Figure 2. Common-Mode Rejection Ratio vs. Frequency
Figure 3. Error Voltage vs. Input Common-Mode Voltage
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)1999-2007 Analog Devices, Inc. All rights reserved.
00783-003
AD629 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Typical Performance Characteristics ............................................. 5 Theory of Operation ........................................................................ 9 Applications..................................................................................... 10 Basic Connections...................................................................... 10 Single-Supply Operation ........................................................... 10 System-Level Decoupling and Grounding.............................. 10 Using a Large Sense Resistor..................................................... 11 Output Filtering.......................................................................... 11 Output Current and Buffering.................................................. 12 A Gain of 19 Differential Amplifier......................................... 12 Error Budget Analysis Example 1 ............................................ 12 Error Budget Analysis Example 2 ............................................ 13 Outline Dimensions ....................................................................... 14 Ordering Guide............................................................................... 15
REVISION HISTORY
3/07--Rev. A to Rev. B Updated Format and Layout .............................................Universal Changes to Ordering Guide .......................................................... 15 3/00--Rev. 0 to Rev. A 10/99--Revision 0: Initial Version
Rev. B | Page 2 of 16
AD629 SPECIFICATIONS
TA = 25C, VS = 15 V, unless otherwise noted. Table 1.
Parameter GAIN Nominal Gain Gain Error Gain Nonlinearity Gain vs. Temperature OFFSET VOLTAGE Offset Voltage vs. Temperature vs. Supply (PSRR) INPUT Common-Mode Rejection Ratio Condition VOUT = 10 V, RL = 2 k Min AD629A Typ Max 1 0.01 4 1 3 0.2 VS = 5 V TA = TMIN to TMAX VS = 5 V to 15 V VCM = 250 V dc TA = TMIN to TMAX VCM = 500 V p-p, dc to 500 Hz VCM = 500 V p-p, dc to 1 kHz Common mode Differential Common mode Differential RL = 10 k RL = 2 k VS = 12 V, RL = 2 k Stable operation 6 100 88 Min AD629B Typ Max 1 0.01 4 1 3 0.1 3 110 96 Unit V/V % ppm ppm ppm/C mV mV V/C dB dB dB dB dB V V k k V V V mA pF kHz V/s kHz s s s V p-p nV/Hz 18 1 V mA mA C
0.05 10 10 1 20 90 86 82 86 270 13
RL = 10 k TA = TMIN to TMAX
0.03 10 3 10 0.5 1 10
84 77 73 77
88
90 270 13 200 800 13 12.5 10
Operating Voltage Range Input Operating Impedance OUTPUT Operating Voltage Range
200 800 13 12.5 10 25 1000 500 2.1 28 15 12 5 15 550 2.5 18 1 2.5 1000
Output Short-Circuit Current Capacitive Load DYNAMIC RESPONSE Small Signal -3 dB Bandwidth Slew Rate Full Power Bandwidth Settling Time
25
1.7 VOUT = 20 V p-p 0.01%, VOUT = 10 V step 0.1%, VOUT = 10 V step 0.01%, VCM = 10 V step, VDIFF = 0 V
1.7
500 2.1 28 15 12 5 15 550
OUTPUT NOISE VOLTAGE 0.01 Hz to 10 Hz Spectral Density, 100 Hz 1 POWER SUPPLY Operating Voltage Range Quiescent Current TEMPERATURE RANGE For Specified Performance
1
VOUT = 0 V TMIN to TMAX TA = TMIN to TMAX -40
0.9 1.2
0.9 1.2 -40
+85
+85
See Figure 19.
Rev. B | Page 3 of 16
AD629 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage, VS Internal Power Dissipation 1 8-Lead PDIP (N) 8-Lead SOIC (R) Input Voltage Range, Continuous Common-Mode and Differential, 10 sec Output Short-Circuit Duration Pin 1 and Pin 5 Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec)
1
Rating 18 V See Figure 4 See Figure 4 300 V 500 V Indefinite -VS - 0.3 V to +VS + 0.3 V 150C -55C to +125C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2.0 TJ = 150C
MAXIMUM POWER DISSIPATION (W)
8-LEAD PDIP 1.5
1.0
Specification is for device in free air: 8-Lead PDIP, JA = 100C/W; 8-Lead SOIC, JA = 155C/W.
8-LEAD SOIC 0.5
00783-004
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE (C)
70
80
90
Figure 4. Maximum Power Dissipation vs. Temperature for SOIC and PDIP
ESD CAUTION
Rev. B | Page 4 of 16
AD629 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VS = 15 V, unless otherwise noted.
100
COMMON-MODE REJECTION RATIO (dB)
400 360
COMMON-MODE VOLTAGE (V)
90 80 70 60 50 40 30 20
00783-006
TA = +25C
320 280 240 200 160 120 80 40 0 0 2 4 6 8 10 12 14 16 POWER SUPPLY VOLTAGE (V) 18
00783-009
TA = +85C TA = -40C
10 0 100 1k 10k 100k FREQUENCY (Hz) 1M
10M
20
Figure 5. Common-Mode Rejection Ratio vs. Frequency
Figure 8. Common-Mode Operating Range vs. Power Supply Voltage
2mV/DIV VS = 18V
RL = 10k
VS = 18V
RL = 2k
OUTPUT ERROR (2mV/DIV)
OUTPUT ERROR (2mV/DIV)
VS = 15V
VS = 15V
VS = 12V
VS = 12V
00783-007
VS = 10V -20 -16 -12 -8 -4 0 4 VOUT (V) 8 12
4V/DIV 16
VS = 10V -20 -16 -12 -8 -4 0 4 VOUT (V) 8 12
4V/DIV 16
20
20
Figure 6. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage, RL = 10 k (Curves Offset for Clarity)
RL = 1k
Figure 9. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage, RL = 2 k (Curves Offset for Clarity)
OUTPUT ERROR (2mV/DIV)
VS = 15V
OUTPUT ERROR (2mV/DIV)
VS = 18V
VS = 5V, RL = 10k
VS = 5V, RL = 2k
VS = 12V
VS = 5V, RL = 1k
00783-008
VS = 10V -20 -16 -12 -8 -4 0 4 VOUT (V) 8 12
4V/DIV 16
VS = 2.5V, RL = 1k -20 -16 -12 -8 -4 0 4 VOUT (V) 8 12
1V/DIV 16
20
20
Figure 7. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage, RL = 1 k (Curves Offset for Clarity)
Figure 10. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage (Curves Offset for Clarity)
Rev. B | Page 5 of 16
00783-011
00783-010
AD629
20V/DIV VS = 15V RL = 10k 40V/DIV VS = 15V RL = 2k
ERROR (0.8ppm/DIV)
00783-012
ERROR (2ppm/DIV)
2.5V/DIV -10 -5 0 VOUT (V) 5 10
2V/DIV -10 -8 -6 -4 -2 0 2 VOUT (V) 4 6 8 10
Figure 11. Gain Nonlinearity; VS = 15 V, RL = 10 k
14.0
20V/DIV VS = 12V RL = 10k
Figure 14. Gain Nonlinearity; VS = 15 V, RL = 2k
-40C 13.0 12.0
OUTPUT VOLTAGE (V)
-40C
ERROR (1ppm/DIV)
11.0 10.0 9.0 -11.5 -12.0 -12.5
VS= 15V
+85C
+25C
-40C +25C 16 18
00783-016
2V/DIV -10 -8 -6 -4 -2 0 2 VOUT (V) 4 6 8 10
00783-013
-13.0 -13.5 +85C 0 2 4 6 8 10 12 14 OUTPUT CURRENT (mA)
Figure 12. Gain Nonlinearity; VS = 12 V, RL =10 k
Figure 15. Output Voltage Operating Range vs. Output Current; VS = 15 V
11.5
40V/DIV
+85C -40C -40C
VS = 5V RL = 1k
10.5 9.5
OUTPUT VOLTAGE (V)
ERROR (6.67ppm/DIV)
8.5 7.5 6.5 -9.0 -9.5 -10.0
VS= 12V
+25C
+85C
-40C +25C +85C 0 2 4 6 8 10 12 14 OUTPUT CURRENT (mA) 16 18
00783-017
0.6V/DIV -3.0 -2.4 -1.8 -1.2 -0.6 0 0.6 VOUT (V) 1.2 1.8 2.4 3.0
00783-014
-10.5 -11.0
Figure 13. Gain Nonlinearity; VS = 5 V, RL = 1 k
Figure 16. Output Voltage Operating Range vs. Output Current; VS = 12 V
Rev. B | Page 6 of 16
00783-015
20
20
AD629
4.5 3.5 2.5
OUTPUT VOLTAGE (V)
+85C -40C -40C +85C VS= 5V +85C -40C +25C +85C 4 6 8 10 12 14 OUTPUT CURRENT (mA) 16 18
00783-018
1.5 0.5
G = +1 RL = 2k CL = 1000pF
+25C
-2.0 -2.5 -3.0 -3.5 -4.0 +25C 0 2
25mV/DIV
4s/DIV
20
Figure 17. Output Voltage Operating Range vs. Output Current; VS = 5 V
120
POWER SUPPLY REJECTION RATIO (dB)
Figure 20. Small Signal Pulse Response
+VS -VS
110 100 90 80 70 60 50 40 30 0.1 1.0 10 100 FREQUENCY (Hz) 1k
00783-019
G = +1 RL = 2k CL = 1000pF
25mV/DIV
4s/DIV
10k
Figure 18. Power Supply Rejection Ratio vs. Frequency
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.01 0.1 1.0 10 100 FREQUENCY (Hz) 1k 10k
00783-020
Figure 21. Small Signal Pulse Response
VOLTAGE NOISE SPECTRAL DENSITY (V/ Hz)
G = +1 RL = 2k CL = 1000pF
5V/DIV
5s/DIV
100k
Figure 19. Voltage Noise Spectral Density vs. Frequency
Figure 22. Large Signal Pulse Response
Rev. B | Page 7 of 16
00783-023
00783-022
00783-021
AD629
5V/DIV +10V VOUT 0V
5V/DIV 0V VOUT -10V
OUTPUT ERROR
1mV = 0.01%
OUTPUT ERROR
1mV = 0.01%
00783-024
1mV/DIV
10s/DIV
1mV/DIV
10s/DIV
Figure 23. Settling Time to 0.01%, for 0 V to 10 V Output Step; G = -1, RL = 2 k
350 300 250 200 150 100 50 0 -150 N = 2180 n 200 PCS. FROM 10 ASSEMBLY LOTS
Figure 26. Settling Time to 0.01% for 0 V to -10 V Output Step; G = -1, RL = 2k
300 N = 2180 n 200 PCS. FROM 10 ASSEMBLY LOTS
250
NUMBER OF UNITS
NUMBER OF UNITS
200
150
100
50
00783-025
00783-027
-100 -50 0 50 100 COMMON-MODE REJECTION RATIO (ppm)
150
0
-900
-600
-300 0 300 OFFSET VOLTAGE (V)
600
900
Figure 24. Typical Distribution of Common-Mode Rejection; Package Option N-8
400 350 300
NUMBER OF UNITS
Figure 27. Typical Distribution of Offset Voltage; Package Option N-8
400
N = 2180 n 200 PCS. FROM 10 ASSEMBLY LOTS
NUMBER OF UNITS
350 300 250 200 150 100
00783-026
N = 2180 n 200 PCS. FROM 10 ASSEMBLY LOTS
250 200 150 100 50 0 -600
-400
-200 0 200 -1 GAIN ERROR (ppm)
400
600
0 -600
-400
-200 0 200 +1 GAIN ERROR (ppm)
400
600
Figure 25. Typical Distribution of -1 Gain Error; Package Option N-8
Figure 28. Typical Distribution of +1 Gain Error; Package Option N-8
Rev. B | Page 8 of 16
00783-029
50
00783-028
AD629 THEORY OF OPERATION
The AD629 is a unity gain, differential-to-single-ended amplifier (diff amp) that can reject extremely high commonmode signals (in excess of 270 V with 15 V supplies). It consists of an operational amplifier (op amp) and a resistor network. To achieve high common-mode voltage range, an internal resistor divider (Pin 3 or Pin 5) attenuates the noninverting signal by a factor of 20. Other internal resistors (Pin 1, Pin 2, and the feedback resistor) restore the gain to provide a differential gain of unity. The complete transfer function equals VOUT = V (+IN) - V (-IN) Laser wafer trimming provides resistor matching so that common-mode signals are rejected while differential input signals are amplified. To reduce output drift, the op amp uses super beta transistors in its input stage. The input offset current and its associated temperature coefficient contribute no appreciable output voltage offset or drift, which has the added benefit of reducing voltage noise because the corner where 1/f noise becomes dominant is below 5 Hz. To reduce the dependence of gain accuracy on the op amp, the open-loop voltage gain of the op amp exceeds 20 million, and the PSRR exceeds 140 dB.
REF(-) 1 -IN 2 +IN 3 -VS 4 21.1k 380k 380k 20k 380k
8 7 6 5
NC +VS OUTPUT REF(+)
00783-001
AD629
NC = NO CONNECT
Figure 29. Functional Block Diagram
Rev. B | Page 9 of 16
AD629 APPLICATIONS
BASIC CONNECTIONS
Figure 30 shows the basic connections for operating the AD629 with a dual supply. A supply voltage of between 3 V and 18 V is applied between Pin 7 and Pin 4. Both supplies should be decoupled close to the pins using 0.1 F capacitors. Electrolytic capacitors of 10 F, also located close to the supply pins, may be required if low frequency noise is present on the power supply. While multiple amplifiers can be decoupled by a single set of 10 F capacitors, each in amp should have its own set of 0.1 F capacitors so that the decoupling point can be located right at the IC's power pins.
+VS REF (-)
1
REF (-)
1
21.1k 380k 380k VY
AD629
8
+VS NC
-IN ISHUNT RSHUNT +IN
2
380k VX
7
+VS
0.1F
3
6
-VS
20k
5
4
REF (+)
OUTPUT = VOUT - VREF
NC = NO CONNECT
VREF
Figure 31. Operation with a Single Supply
21.1k 380k 380k
AD629
8
+3V TO +18V NC
-IN ISHUNT RSHUNT +IN
2
380k
7
+VS
0.1F
(SEE TEXT)
3
6
VOUT = ISHUNT x RSHUNT REF (+)
-VS (SEE TEXT) 0.1F
20k
4 5
Figure 30. Basic Connections
00783-030
NC = NO CONNECT -VS -3V TO -18V
Applying a reference voltage to REF(+) and REF(-) and operating on a single supply reduces the input common-mode range of the AD629. The new input common-mode range depends upon the voltage at the inverting and noninverting inputs of the internal operational amplifier, labeled VX and VY in Figure 31. These nodes can swing to within 1 V of either rail. Therefore, for a (single) supply voltage of 10 V, VX and VY can range between 1 V and 9 V. If VREF is set to 5 V, the permissible common-mode range is +85 V to -75 V. The common-mode voltage ranges can be calculated by VCM () = 20 VX/VY() - 19 VREF
The differential input signal, which typically results from a load current flowing through a small shunt resistor, is applied to Pin 2 and Pin 3 with the polarity shown to obtain a positive gain. The common-mode range on the differential input signal can range from -270 V to +270 V, and the maximum differential range is 13 V. When configured as shown in Figure 30, the device operates as a simple gain-of-1, differential-to-singleended amplifier; the output voltage being the shunt resistance times the shunt current. The output is measured with respect to Pin 1 and Pin 5. Pin 1 and Pin 5 (REF(-) and REF(+)) should be grounded for a gain of unity and should be connected to the same low impedance ground plane. Failure to do this results in degraded commonmode rejection. Pin 8 is a no connect pin and should be left open.
SYSTEM-LEVEL DECOUPLING AND GROUNDING
The use of ground planes is recommended to minimize the impedance of ground returns (and therefore the size of dc errors). Figure 32 shows how to work with grounding in a mixed-signal environment, that is, with digital and analog signals present. To isolate low level analog signals from a noisy digital environment, many data acquisition components have separate analog and digital ground returns. All ground pins from mixed-signal components, such as ADCs, should return through a low impedance analog ground plane. Digital ground lines of mixed-signal converters should also be connected to the analog ground plane. Typically, analog and digital grounds should be separated; however, it is also a requirement to minimize the voltage difference between digital and analog grounds on a converter, to keep them as small as possible (typically <0.3 V). The increased noise, caused by the converter's digital return currents flowing through the analog ground plane, is typically negligible. Maximum isolation between analog and digital is achieved by connecting the ground planes back at the supplies. Note that Figure 32 suggests a "star" ground system for the analog circuitry, with all ground lines being connected, in this case, to the ADC's analog ground. However, when ground planes are used, it is sufficient to connect ground pins to the nearest point on the low impedance ground plane.
SINGLE-SUPPLY OPERATION
Figure 31 shows the connections for operating the AD629 with a single supply. Because the output can swing to within only about 2 V of either rail, it is necessary to apply an offset to the output. This can be conveniently done by connecting REF(+) and REF(-) to a low impedance reference voltage (some ADCs provide this voltage as an output), which is capable of sinking current. Therefore, for a single supply of 10 V, VREF may be set to 5 V for a bipolar input signal. This allows the output to swing 3 V around the central 5 V reference voltage. Alternatively, for unipolar input signals, VREF can be set to about 2 V, allowing the output to swing from 2 V (for a 0 V input) to within 2 V of the positive rail.
Rev. B | Page 10 of 16
00783-031
AD629
ANALOG POWER SUPPLY -5V +5V GND 0.1F 0.1F 0.1F
4 7 1 6 14
DIGITAL POWER SUPPLY GND +5V
0.1F
Table 3 shows some sample error voltages generated by a common-mode voltage of 200 V dc with shunt resistors from 20 to 2000 . Assuming that the shunt resistor is selected to use the full 10 V output swing of the AD629, the error voltage becomes quite significant as RSHUNT increases. Table 3. Error Resulting from Large Values of RSHUNT (Uncompensated Circuit)
RS () 20 1000 2000 Error VOUT (V) 0.01 0.498 1 Error Indicated (mA) 0.5 0.498 0.5
+IN -IN
-VS
3 2
+VS OUTPUT 6
4 3
VDD AGND DGND VIN1 VIN2
12
GND
VDD
AD629
1
AD7892-2
MICROPROCESSOR
00783-032
REF(-) REF(+)
5
Figure 32. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies
POWER SUPPLY GND +5V 0.1F 0.1F 0.1F
7 4
To measure low current or current near zero in a high commonmode environment, an external resistor equal to the shunt resistor value can be added to the low impedance side of the shunt resistor, as shown in Figure 34.
REF (-)
1
+IN -IN
3 2
+VS
-VS OUTPUT 6
VDD VIN1 VIN2
AGND DGND VDD GND
21.1k 380k 380k
AD629
8
+VS NC
AD629
1
00783-033
REF(-) REF(+)
5
ADC
MICROPROCESSOR
RCOMP ISHUNT RSHUNT
-IN +IN
2
380k
7
+VS
0.1F VOUT
3
6
Figure 33. Optimal Ground Practice in a Single-Supply Environment
If there is only a single power supply available, it must be shared by both digital and analog circuitry. Figure 33 shows how to minimize interference between the digital and analog circuitry. In this example, the ADC's reference is used to drive Pin REF(+) and Pin REF(-). This means that the reference must be capable of sourcing and sinking a current equal to VCM/200 k. As in the previous case, separate analog and digital ground planes should be used (reasonably thick traces can be used as an alternative to a digital ground plane). These ground planes should connect at the power supply's ground pin. Separate traces (or power planes) should run from the power supply to the supply pins of the digital and analog circuits. Ideally, each device should have its own power supply trace, but these can be shared by a number of devices, as long as a single trace is not used to route current to both digital and analog circuitry.
-VS -VS 0.1F
20k
4 5
REF (+)
00783-034
NC = NO CONNECT
Figure 34. Compensating for Large Sense Resistors
OUTPUT FILTERING
A simple 2-pole, low-pass Butterworth filter can be implemented using the OP177 after the AD629 to limit noise at the output, as shown in Figure 35. Table 4 gives recommended component values for various corner frequencies, along with the peak-topeak output noise for each case.
REF (-)
1
21.1k 380k 380k
AD629
8
+VS NC 0.1F
7
+VS C1 0.1F VOUT
-IN +IN -VS 0.1F
2
380k
+VS R1 R2 C2
OP177
USING A LARGE SENSE RESISTOR
Insertion of a large value shunt resistance across the input pins, Pin 2 and Pin 3, will imbalance the input resistor network, introducing a common-mode error. The magnitude of the error will depend on the common-mode voltage and the magnitude of RSHUNT. Table 4. Recommended Values for 2-Pole Butterworth Filter
Corner Frequency No Filter 50 kHz 5 kHz 500 Hz 50 Hz R1 2.94 k 1% 2.94 k 1% 2.94 k 1% 2.7 k 10% R2 1.58 k 1% 1.58 k 1% 1.58 k 1% 1.5 k 10% C1
3
6
0.1F
20k
4 5
REF (+) -VS
00783-035
NC = NO CONNECT
Figure 35. Filtering of Output Noise Using a 2-Pole Butterworth Filter
C2 1 nF 10% 10 nF 10% 0.1 F 10% 1 F 20%
Output Noise (p-p) 3.2 mV 1 mV 0.32 mV 100 V 32 V
2.2 nF 10% 22 nF 10% 220 nF 10% 2.2 F 20%
Rev. B | Page 11 of 16
AD629
OUTPUT CURRENT AND BUFFERING
The AD629 is designed to drive loads of 2 k to within 2 V of the rails but can deliver higher output currents at lower output voltages (see Figure 15). If higher output current is required, the output of the AD629 should be buffered with a precision op amp, such as the OP113, as shown in Figure 36. This op amp can swing to within 1 V of either rail while driving a load as small as 600 .
REF (-)
1
ERROR BUDGET ANALYSIS EXAMPLE 1
In the dc application that follows, the 10 A output current from a device with a high common-mode voltage (such as a power supply or current-mode amplifier) is sensed across a 1 shunt resistor (see Figure 38). The common-mode voltage is 200 V, and the resistor terminals are connected through a long pair of lead wires located in a high noise environment, for example, 50 Hz/60 Hz, 440 V ac power lines. The calculations in Table 5 assume an induced noise level of 1 V at 60 Hz on the leads, in addition to a full-scale dc differential voltage of 10 V. The error budget table quantifies the contribution of each error source. Note that the dominant error source in this example is due to the dc common-mode voltage.
OUTPUT CURRENT 10 AMPS 200V CMDC TO GROUND 1 SHUNT REF (-)
1
21.1k 380k 380k
AD629
8
+VS NC 0.1F
7
-IN +IN -VS 0.1F
2
380k
0.1F VOUT
3
6 OP113
20k
4 5
REF (+)
0.1F
NC = NO CONNECT
-VS
00783-036
21.1k 380k 380k
AD629
8
NC +VS 0.1F
Figure 36. Output Buffering Application
-IN +IN
2
380k
7
A GAIN OF 19 DIFFERENTIAL AMPLIFIER
While low level signals can be connected directly to the -IN and +IN inputs of the AD629, differential input signals can also be connected, as shown in Figure 37, to give a precise gain of 19. However, large common-mode voltages are no longer permissible. Cold junction compensation can be implemented using a temperature sensor, such as the AD590.
REF (-)
1
3
6
VOUT REF (+)
00783-038
60Hz POWER LINE
-VS
20k
4 5
0.1F NC = NO CONNECT
Figure 38. Error Budget Analysis Example 1: VIN = 10 V Full-Scale, VCM = 200 V DC, RSHUNT = 1 , 1 V p-p, 60 Hz Power-Line Interference
21.1k 380k 380k
AD629
8
+VS NC
THERMOCOUPLE
-IN +IN
2
380k
7
+VS
0.1F VOUT
3
6
VREF
4
20k
5
REF (+)
00783-037
NC = NO CONNECT
Figure 37. A Gain of 19 Thermocouple Amplifier
Table 5. AD629 vs. INA117 Error Budget Analysis Example 1 (VCM = 200 V dc)
Error Source ACCURACY, TA = 25C Initial Gain Error Offset Voltage DC CMR (Over Temperature) TEMPERATURE DRIFT (85C) Gain Offset Voltage RESOLUTION Noise, Typical, 0.01 Hz to 10 Hz, V p-p CMR, 60 Hz Nonlinearity AD629 (0.0005 x 10)/10 V x 106 (0.001 V/10 V) x 106 (224 x 10-6 x 200 V)/10 V x 106 INA117 (0.0005 x 10)/10 V x 106 (0.002 V/10 V) x 106 (500 x 10-6 x 200 V)/10 V x 106 Total Accuracy Error 10 ppm/C x 60C (40 V/C x 60C) x 106/10 V Total Drift Error 25 V/10 V x 106 (500 x 10-6 x 1 V)/10 V x 106 (10-5 x 10 V)/10 V x 106 Total Resolution Error Total Error Error, ppm of FS AD629 INA117 500 100 4480 5080 600 120 720 2 14 10 26 5826 500 200 10,000 10,700 600 240 840 3 50 10 63 11,603
10 ppm/C x 60C (20 V/C x 60C) x 106/10 V
15 V/10 V x 106 (141 x 10-6 x 1 V)/10 V x 106 (10-5 x 10 V)/10 V x 106
Rev. B | Page 12 of 16
AD629
ERROR BUDGET ANALYSIS EXAMPLE 2
This application is similar to the previous example except that the sensed load current is from an amplifier with an ac common-mode component of 100 V (frequency = 500 Hz) present on the shunt (see Figure 39). All other conditions are the same as before. Note that the same kind of power-line interference can happen as detailed in Example 1. However, the ac common-mode component of 200 V p-p coming from the shunt is much larger than the interference of 1 V p-p; therefore, this interference component can be neglected.
OUTPUT CURRENT 10 AMPS 100V AC CM TO GROUND 1 SHUNT REF (-)
1
21.1k 380k 380k
AD629
8
NC +VS 0.1F
-IN +IN
2
380k
7
3
6
VOUT REF (+)
00783-039
60Hz POWER LINE
-VS
20k
4 5
0.1F NC = NO CONNECT
Figure 39. Error Budget Analysis Example 2: VIN = 10 V Full-Scale, VCM = 100 V at 500 Hz, RSHUNT =1
Table 6. AD629 vs. INA117 AC Error Budget Example 2 (VCM = 100 V @ 500 Hz)
Error Source ACCURACY, TA = 25C Initial Gain Error Offset Voltage TEMPERATURE DRIFT (85C) Gain Offset Voltage RESOLUTION Noise, Typical, 0.01 Hz to 10 Hz, V p-p CMR, 60 Hz Nonlinearity AC CMR @ 500 Hz AD629 (0.0005 x 10)/10 V x 106 (0.001 V/10 V) x 106 INA117 (0.0005 x 10)/10 V x 106 (0.002 V/10 V) x 106 Total Accuracy Error 10 ppm/C x 60C (40 V/C x 60C) x 106/10 V Total Drift Error 25 V/10 V x 106 (500 x 10-6 x 1 V)/10 V x 106 (10-5 x 10 V)/10 V x 106 (500 x 10-6 x 200 V)/10 V x 106 Total Resolution Error Total Error Error, ppm of FS AD629 INA117 500 100 600 600 120 720 2 14 10 2820 2846 4166 500 200 700 600 240 840 3 50 10 10,000 10,063 11,603
10 ppm/C x 60C (20 V/C x 60C) x 106/10 V
15 V/10 V x 106 (141 x 10-6 x 1 V)/10 V x 106 (10-5 x 10 V)/10 V x 106 (141 x 10-6 x 200 V)/10 V x 106
Rev. B | Page 13 of 16
AD629 OUTLINE DIMENSIONS
0.400 (10.16) 0.365 (9.27) 0.355 (9.02)
8 1 5
4
0.280 (7.11) 0.250 (6.35) 0.240 (6.10)
0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14)
0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
0.015 (0.38) MIN SEATING PLANE 0.005 (0.13) MIN
0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX
0.014 (0.36) 0.010 (0.25) 0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 40. 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters)
5.00 (0.1968) 4.80 (0.1890)
4.00 (0.1574) 3.80 (0.1497)
8 1
5 4
6.20 (0.2441) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 45 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 41. 8-Lead Standard Small Outline Package [SOIC_N] (R-8) Dimensions shown in millimeters and (inches)
Rev. B | Page 14 of 16
012407-A
070606-A
AD629
ORDERING GUIDE
Model AD629AN AD629ANZ 1 AD629AR AD629AR-REEL AD629AR-REEL7 AD629ARZ1 AD629ARZ-RL1 AD629ARZ-R71 AD629BN AD629BNZ1 AD629BR AD629BR-REEL AD629BR-REEL7 AD629BRZ1 AD629BRZ-RL1 AD629BRZ-R71 AD629-EVAL
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces 8-Lead SOIC_N 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces Evaluation Board
Package Option N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8
Z = RoHS compliant part.
Rev. B | Page 15 of 16
AD629 NOTES
(c)1999-2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00783-0-2/07(B)
Rev. B | Page 16 of 16

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